1. Technical Field
The present invention relates to a stack type semiconductor chip package and a fabrication method thereof, and more particularly, to a stack type semiconductor chip package having different types of chips, and a fabrication method thereof.
2. Description of the Related Art
As a variety of semiconductor products are developed, a stack type semiconductor chip package (for instance, a multichip package (MCP)) or a system in package (SIP), including different types of chips stacked on top of one another, are being used for a semiconductor package.
FIG. 1 is a cross-sectional view illustrating one example of a conventional stack type semiconductor chip package.
Specifically, the conventional stack type semiconductor chip package includes different types of chips 12, 14 and 16 stacked on a printed circuit board (PCB) 10 and on top of one another, using adhesive layers 13. The different types of chips 12, 14 and 16 have different functions and sizes, and may be memory circuit chips or logic circuit chips. The different types of chips 12, 14 and 16 are electrically connected to the PCB 10 using bonding wires 18. Thus, the different types of chips 12, 14 and 16 are indirectly connected to one another using the PCB 10. The different types of chips 12, 14 and 16 on the PCB 10, and the bonding wires 18 are encapsulated by an encapsulating material 26 such as an epoxy resin. Vias 22 are formed in the PCB 10, and are connected to solder balls 20, which are external connection terminals, through connection pads.
However, performance improvement of the conventional stack type semiconductor chip package of FIG. 1 is limited since the different types of chips 12, 14 and 16 are indirectly connected to one another through the PCB 10 using the bonding wires 18. Also, the connection of the different types of chips 12, 14 and 16 to the PCB 10 using the bonding wires 18 makes miniaturization of the package difficult. Furthermore, the stack type semiconductor chip package of FIG. 1 cannot be used as an image sensor chip package because image sensor chip packages are sensitive to impurity particles due to factors related to the packaging process.
FIG. 2 is a cross-sectional view illustrating another example of a conventional stack type semiconductor chip package.
Specifically, the conventional stack type semiconductor chip package includes different types of chips 34, 36 and 38 on a PCB 30, using an interposer chip 32 interposed therebetween. The different types of chips 34, 36 and 38 have different functions and sizes, and may be memory circuit chips or logic circuit chips. The different types of chips 34, 36, and 38 are electrically connected to second pads 44 of the PCB 30 through first pads 41, first vias 40, and connection balls 42. Thus, the different types of chips 34, 36, and 38 are directly connected to one another through the first vias 40 and the first pads 41 that are formed in each chip. Particularly, the different types of chips 34, 36 and 38 are directly connected through the first vias 40 in the chips. The second pads 44 are connected to solder balls 48 through second vias 46 and third pads 47 in the PCB 30.
Unlike the stack type semiconductor chip package of FIG. 1, the stack type semiconductor chip package of FIG. 2 is advantageous in performance improvement and package miniaturization, since the different types of chips 34, 36, and 38 are directly connected without using the bonding wires. However, the stack type semiconductor chip package of FIG. 2 has an undesirably complex rewiring layout. Also, the first vias 40 in the different types of chips 34, 36 and 38 significantly lower a fabrication yield of the different types of chips. Additionally, the stack type semiconductor chip package of FIG. 2 must disadvantageously employ the interposer chip 32.
The stack type semiconductor chip package of FIG. 2 has many structural problems such as structural instability resulting from stacking larger chips 36 and 38 on a smaller chip 34. The stack type semiconductor chip package of FIG. 2 also cannot be used for an image sensor chip package that is sensitive to impurity particles such as dust because of factors related to the packaging process. The present invention addresses these and other disadvantages of the conventional art.